The present invention relates to technology for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device which uses a dual damascene process.
As a degree of integration of a semiconductor device increases, a new trial of using copper (Cu) instead of aluminum (Al) or tungsten (W) as a material for metallization has continued since the resistivity of the copper is approximately 60% of that of the aluminum.
However, since it is difficult to etch the copper, a damascene process is introduced to overcome the problem.
The damascene process is technology of forming a trench in a region where a line is to be formed through a photolithography process for a dielectric layer and then filling the trench with a conducting material such as Al, W and Cu for the line formation, thereby forming a line in a shape of the trench.
Recently, a dual damascene process has been introduced. Thus, a trench for the line formation as well as a via hole connecting an upper line and a lower line can be formed through the dual damascene process. The dual damascene process is classified into a via first scheme and a trench first scheme.
FIGS. 1A to 1D illustrate cross-sectional view explaining a dual damascene process having the via first scheme according to the prior art.
Referring to FIG. 1A, an inter-layer dielectric layer 11 is formed on a conducting layer 10. The conducting layer 10 may include a plug, a metal line or a semiconductor substrate.
Then, a first photoresist pattern 12 for forming a via hole is formed on the inter-layer dielectric layer 11. Herein, a reference numeral ‘V’ represents a region where the via hole is to be formed.
Referring to FIG. 1B, after forming the via hole 13 exposing the conducting layer 10 by etching the inter-layer dielectric layer 11 using the first photoresist pattern 12 as an etch barrier, the first photoresist pattern 12 is removed.
Referring to FIG. 1C, an anti-reflection layer 14 is formed to have a thickness as much as filling the via hole 13 on a whole surface of a resultant structure including the via hole 13. The anti-reflection layer 14 prevents the light from being reflected in an exposure process of the photoresist and, at the same time, serves as a barrier to prevent the conducting layer 10 exposed according to the formation of the via hole 13 from being damaged.
Subsequently, a second photoresist pattern 15 used for forming a trench is formed on the anti-reflection layer 14. Herein, a reference numeral ‘T’ represents a region where the trench is to be formed and the via hole 13 is overlapped with the region T. That is, the via hole 13 is disposed under the region T.
Referring to FIG. 1D, the trench 16 is formed by etching the inter-layer dielectric layer 11 up to a certain depth using the second photoresist pattern 15 as an etch barrier. As a result, a dual damascene pattern 100 including the trench 16 and the via hole 13 overlapped within the trench 16 is formed in the inter-layer dielectric layer 11.
Then, although it is not shown, a line having a shape of the dual damascene pattern 100 may be formed in the inter-layer dielectric layer 11 by depositing a conducting layer for the line formation such as copper on a whole surface of a resultant structure including the dual damascene pattern 100 and performing a planarization process such as a chemical mechanical polishing (CMP) process until the inter-layer dielectric layer 11 is exposed.
However, the dual damascene process of the via first scheme has following problems.
As described in a part X of FIG. 1C, the non-uniformity of a thickness of the anti-reflection layer 14 occurs in an edge region of the inter-layer dielectric layer 11 where the via hole 13 is formed during the process of forming the anti-reflection layer 14. Thus, since the inter-layer dielectric layer 11 around the via hole 13 collapses in the process of forming the trench 16 as shown in a part Y of FIG. 1D, it is difficult to obtain a desired profile of the trench 16 that is designated by a dotted line. Since this phenomenon makes the deposition of the conducting layer for the line formation unstable, a defect may occur or the line may be cut in the CMP process. Consequently, the above problems cause an electrical failure of a device and thus may deteriorate the reliability of the device.